1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to a semiconductor memory device that takes in an external command in synchronization with an external clock signal and in synchronization with an internal clock signal, and makes a transition among a plurality of operation states corresponding to the taken external command.
2. Description of the Background Art
A semiconductor memory device receives various commands from the outside, generates various internal control signals in accordance with these commands, and controls internal circuitry in accordance with these internal control signals, so that internal operations including data writing and reading operations are executed.
Here, the semiconductor memory device takes in an external command in synchronization with an external clock signal of a prescribed period, and generates an external control signal in response to the taken external command, using an external control signal generating circuit provided therein. Further, when the external control signal is taken into an internal control signal generating circuit in synchronization with an internal clock signal, an internal control signal, for example, a signal for writing data to a memory cell array or for erasing data from the memory cell array, is generated in response. A control circuit operates the internal circuitry in response to the internal control signal.
In a semiconductor memory device, it takes a prescribed time period from the external command is received until a prescribed operation corresponding to the command is completed. Among the semiconductor memory devices, a flash memory, which is a non-volatile memory allowing electrical data writing and data reading, requires a longer time period for data writing, and therefore, the prescribed time period naturally becomes longer in the flash memory as compared with other semiconductor memory devices.
In view of the foregoing, in a semiconductor memory device, it is a general approach to receive as inputs external commands in synchronization with the external clock signal, and to perform internal operations in synchronization with the internal clock signal that is not synchronized with the external clock signal, generated by an internal oscillation circuit. In this approach, when an output of a circuit synchronized with the external clock signal is to be input to a circuit synchronized with the internal clock signal or vise-versa, the timing of receiving the external command and the timing of the internal operation must be adjusted not to be overlapped with each other, in order to avoid any malfunction.
By way of example, a malfunction may occur when an external command for executing a reading or writing operation clashes with an internal command for executing a refresh operation in a DRAM (Dynamic Random Access Memory), or when a data writing operation controlled by a CPU (Central Processing Unit) conflicts with a data reading operation controlled by a communication gate array in a single port RAM. Techniques for preventing data destruction or communication failure caused by such malfunctions are disclosed, for example, in Japanese Patent Laying-Open Nos. 2002-304885 and 09-311811. These techniques, however, address situations where a single clock signal is supplied, and not necessarily intended for the semiconductor memory device described above in which asynchronous two clock signals are supplied.
As described above, in the conventional semiconductor memory device to which two clock signals not synchronized with each other are supplied, it is indispensable to adjust timings of the external command and the internal control signal. Actually, however, an external command is input to an external control signal generating circuit even in the period of an internal operation.
By way of example, when the internal operation ends, a reset signal for initializing an internal latch circuit or the like is input from the internal control signal generating circuit to the external control signal generating circuit. If an external command is input in a period in which the external control signal generating circuit is reset in response to the reset signal in non-synchronized manner, a logical mismatch occurs in the external control signal generating circuit, possibly resulting in a malfunction.
Further, the external control signal generating circuit and the internal control signal generating circuit are respectively synchronized with clock signals that are asynchronous with each other, and therefore, when control signals are transferred between these circuits, a meta stable state, in which an output signal becomes unstable, may possibly occur in a sequential circuit such as a flip-flop contained therein. When a meta-stable state occurs, in the control signal generating circuits, the unstable state is propagated to a logic circuit and the like in succeeding stages, possibly hindering a normal operation.